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rfx

rfx is a 3-D finite-difference time-domain (FDTD) electromagnetic simulator built in JAX. These docs focus on maintained user workflows with explicit support boundaries.

Start with the uniform Cartesian Yee FDTD solver. The table summarizes the documented workflows and their limits:

ConfigurationDocumented use
Uniform Yee RF workflowsrecommended default for tutorials, examples, probes, Harminv, selected S-parameter calculations, and far-field calculations
Rectangular waveguide S-matricesvalidated within the documented rectangular-guide geometry, mesh, and frequency limits
Lumped, wire, and microstrip-line port workflowsavailable through their matching calculators; validation scope follows the support matrix
Coaxial line reflectionfloat32 precision, nonperiodic 3D second-order uniform Yee grid, CPML on all six boundary faces with positive thickness on both z faces, cpml_axes="z", and exactly one face="top" coaxial port; see Sources and Ports for the self-contained calculator limits
Differentiable design loopsuse proxy objectives, gradient checks, and documented validation before treating a design result as evidence
Studio, CLI, and MCP experimentsversioned local CPU runs, append-only revisions, replay bundles, and server-approved MCP actions; see the guide for the current UI scope

If a capability is not listed here or on the Support Boundaries page, treat it as outside the documented public support scope until that page lists it.


FeatureDetail
GPU accelerationJAX/JIT execution for large 3-D grids
Differentiable workflowsjax.grad through selected JAX-traced objectives; validate the final RF observable within its documented limits
RF workflow toolsmaterials, sources, probes, ports, S-parameter helpers, Harminv, far-field utilities
Recommended examplesthe ordered tutorials under examples/tutorials/ (start at examples/README.md), plus the inverse-design examples
Documented limitssupport follows the stated geometry, mesh, frequency, and calculator constraints, not every importable symbol

Terminal window
pip install rfx-fdtd

GPU support depends on your JAX/CUDA environment:

Terminal window
pip install "jax[cuda12]" rfx-fdtd

from rfx import Box, GaussianPulse, Simulation
sim = Simulation(
freq_max=5e9,
domain=(0.14, 0.06, 0.05),
dx=2e-3,
boundary="cpml",
cpml_layers=8,
)
sim.add_material("slab", eps_r=2.2, sigma=0.01)
sim.add(Box((0.07, 0.018, 0.018), (0.09, 0.042, 0.032)), material="slab")
sim.add_source(
(0.03, 0.03, 0.025),
"ez",
waveform=GaussianPulse(f0=3e9, bandwidth=0.8),
)
sim.add_probe((0.11, 0.03, 0.025), "ez")
preflight = sim.preflight()
print(preflight.format())
preflight.raise_for_failure()
result = sim.run(n_steps=1200)
print(result.time_series.shape)

This records a dielectric pulse response without making a resonance or Q claim. Resolve any preflight warning introduced by model changes. Use the First Patch tutorial for a patch model that passes preflight and the checks required before reporting resonance or Q.


  • Simulation APISimulation, Result, auto_configure, ports, NTFF, and design helpers
  • Materials & Geometry — library materials, Debye/Lorentz, CSG shapes, PCB stackup
  • Sources & Ports — point sources, lumped/wire ports, microstrip-line ports, waveguide ports, and coaxial-line reflection for exactly one face="top" port within its stated limits
  • Probes & S-Parameters — DFT probes, S-matrix helpers, Harminv, de-embedding, exports
  • Memory Reduction — reduce FDTD/AD memory while preserving validation boundaries
  • ADI Solver (experimental) — unconditionally stable ADI-FDTD for stiff meshes, its timestep-vs-accuracy trade, and what is validated
  • Waveguide Ports — rectangular waveguide modal workflows
  • Examples — recommended public runnable paths
  • Validation — public support and validation overview
  • Gallery — examples with their RF evidence and limits stated on each page
  • API — curated public API contract