Reference Lane
Recommended default lane
Section titled “Recommended default lane”Start with the uniform Cartesian Yee RF/FDTD lane:
- PEC, CPML, or bounded UPML boundaries
- point/current sources
- lumped and wire ports
- specialized microstrip-line and rectangular waveguide workflows where documented
- probes, flux monitors, Harminv resonance extraction, selected S-parameter workflows, and benchmarked far-field workflows
This is the lane to use first for ordinary RF examples and public tutorials.
Experimental / under active validation
Section titled “Experimental / under active validation”The following surfaces are real and useful, but should be treated as narrower than the default lane:
| Surface | Public status |
|---|---|
| non-uniform mesh | useful for thin-substrate experiments; not the default claim lane |
| distributed execution | scaling lane; check feature combinations before use |
| Floquet/Bloch | experimental periodic/unit-cell workflow |
| SBP-SAT subgridding | research/experimental local mesh refinement |
| coaxial and advanced port workflows | under active calibration and validation |
| inverse-design extensions | available for selected workflows; check examples and limitations |
S-parameter API boundaries
Section titled “S-parameter API boundaries”run(compute_s_params=True)is the full S-matrix API for lumped/wireadd_port(...)workflows.compute_msl_s_matrix()is the microstrip-line S-matrix API.compute_waveguide_s_matrix()is the rectangular waveguide S-matrix API.- Coaxial and Floquet surfaces are experimental and should not be presented as the default S-parameter path.
Practical rule
Section titled “Practical rule”If a feature is not in the recommended default lane, call it experimental or under active validation and point users to the current example or limitation page.